Semiconductor integrated circuit device and production method thereof

ABSTRACT

A CVD device ( 100 ) used for depositing a silicon nitride has a structure in which a hot wall furnace ( 103 ) for thermally degrading a source gas and a chamber ( 101 ) for forming a film over a surface of a wafer ( 1 ) are separated from each other. The hot wall furnace ( 103 ) for thermally degrading the source gas is provided above the chamber ( 101 ), and a heater ( 104 ) capable of setting the inside of the furnace at a high temperature atmosphere of approximately 1200° C. is provided at the outer periphery thereof. The source gas, supplied to the hot wall furnace ( 103 ) through pipes ( 105 ) and ( 106 ), is thermally degraded in this furnace in advance, and degraded components thereof are supplied on a stage ( 102 ) of the chamber ( 101 ) to form a film on the surface of the wafer ( 1 ).

TECHNICAL FILED OF THE INVENTION

The present invention relates to a semiconductor integrated circuitdevice and its manufacturing technique and, particularly, to a techniqueeffectively applied to a semiconductor integrated circuit device havingthe step of depositing a silicon nitride on a substrate by using a CVD(Chemical Vapor Deposition) device.

BACKGROUND OF THE INVENTION

In a process of manufacturing a fine and highly integrated LSI in recentyears, a difference between the etching rates of a silicon oxide and asilicon nitride is utilized to form a shallow groove isolation (SGI)over a silicon substrate or to form a contact hole for the gateelectrode of a MISFET (Metal Insulator Semiconductor Field EffectTransistor) in a self-align manner. A forming method for the shallowgroove isolation (SGI) is described in Japanese Patent Laid-Open No11-16999 and the like, for example. Further, a forming method for aself-align contact (SAC) is described in 11-17147 and the like, forexample.

The silicon nitride, used in the forming step of a shallow grooveisolation or the forming step of a self-align contact described above,is generally formed by the CVD method using, as a source gas, a silanetype gas such as monosilane (SiH₄) or the like and ammonia (NH₃) ornitrogen (N₂). However, it is known that a large amount of hydrogen,derived from the source gas, is taken into this silicon.

A Japanese Patent Laid-open No. 2000-58483 gazette (Mine et al.) pointsout the problem that when a silicon nitride, serving as a stopper filmof a self-align contact, is deposited at an upper portion and a side ofa gate electrode containing a p-type polycrystal silicon, boron (B),serving as a dopant in the p-type polycrystal silicon, is diffused intoa gate insulator or a silicon substrate, whereby a flat band voltage(Vfb) or a threshold voltage (Vth) is varied and reliability of the gateinsulator is degraded. Such problem is caused by the fact that hydrogen,derived from a material gas contained in the silicon nitride, increasesdiffusion of boron (enhanced diffusion).

This gazette discloses, as a measure for solving the above problem, atechnique for suppressing the enhanced diffusion of boron, by depositinga silicon nitride using a source gas without hydrogen and by reducingthe concentration of hydrogen in the film to 1×10²¹ atoms/cc or less.There is exemplified a mixed gas of a halogen compound of silicon, suchas SiF₄, SiCl₄, SiBr₄, and SiI₄, and nitrogen, as the source gas withouthydrogen.

A Japanese Patent Laid-open NO. 2000-114257 gazette (Matsuoka et al.)points out the problem that since a silicon nitride, deposited by aplasma CVD method using monosilane (SiH₄) and nitrogen, has a largeamount of hydrogen taken therein, to use this film as a gate insulatorcause a harmful influence such as degradation of hot carrier, increasein leak current, or the like. Meanwhile, it also points out the problemthat when a halogen compound of silicon such as SiF₄ is used instead ofmonosilane, hydrogen is not taken in the film, but a large amount ofhalogen is taken therein, which causes trap site increase.

This gazette discloses, as a measure for solving the above problem, atechnique for forming a silicon nitride containing a small amount ofhydrogen or halogen, by exciting at least one of silicon tetrafluoride(SiF₂) and nitrogen and by supplying it to a substrate. As a method forobtaining excited silicon difluoride, there is disclosed a method forelectrically exciting silicon tetrafluoride (SiF₄) by microwavedischarge or for bringing silicon tetrafluoride into contact with a massof heated Si. Further, as a method for supplying the excited gas to thesubstrate, there is disclosed a method for, before such two gases areput into a reaction chamber, mixing the gases in a preliminary chamber,which is provided for mixing these gases and is different from thereaction chamber, and thereafter supplying the mixed gases to thereaction chamber.

A Japanese Patent Laid-open No. 11-46000 gazette (Sakamoto) discloses atechnique for manufacturing a thin film transistor using polycrystalsilicon as a semiconductor region, wherein when a gate insulator and aninterlayer insulator are formed over a polycrystal silicon, the gateinsulator is made of a silicon oxide and the interlayer insulator ismade of a silicon nitride, thereby reducing an overetching amount of thepolycrystal silicon in the step of dry-etching the two insulators and offorming a contact hole reaching a thin polycrystal silicon.

Further, this gazette teaches the structure in which the aboveinterlayer insulator is constituted by: an underlying silicon nitridehaving a high hydrogen containing rate; and an upper silicon nitridehaving a low hydrogen containing rate. When the hydrogen containing rateof the underlying silicon nitride is increased, a large amount ofhydrogen is supplied into the polycrystal silicon and, therefore,crystal faults of the polycrystal silicon are decreased and thetransistor characteristics are improved. Meanwhile, when the hydrogencontaining rate of the upper silicon nitride is reduced, a fine filmhaving less pin holes in number is obtained and, therefore, a dielectricstrength of the transistor is improved.

The above-mentioned two silicon nitrides having the different hydrogencontaining rates are continuously deposited by using a plasma CVDdevice. The underlying silicon nitride having a high hydrogenconcentration is deposited by lowering a substrate temperature (250°C.), and the upper silicon nitride having a low hydrogen concentrationis deposited by increasing a substrate temperature (390° C.).

A Japanese Patent Laid-open No. 9-289209 gazette (Sonoda et al.)discloses a technique for setting, to 0.6×10²¹ atoms/cm⁻³ or less, abonding amount of Si—H in a silicon nitride used as an interlayerinsulator or a passivation film to restrict generation of electron trapin a gate oxide film or a tunnel oxide film and to prevent variation inthreshold values of a transistor. The above-mentioned silicon nitride isdeposited by a plasma CVD method, which uses a gas having a Si—H bondsuch as monosilane (SiH₄) or dichlorosilane (Si₂H₆).

A Japanese Patent Laid-open No. 2000-340562 gazette (Itoh et al.) pointsout the problem of negative bias temperature instability (NBTI) in whicha threshold voltage of a MISFET is varied due to an influence onhydrogen contained in a silicon nitride used for a final protective film(final passivation film) or the like, thereby reducing a lifetime of adevice product.

This gazette proposes to use a silicon nitride such that a Si—H bond isemployed as a main structure and a Si—NH₂ bond is employed as asub-structure and an integral intensity of the peak of the Si—N bondintensity by a FTIR (Fourier Transform Infrared Spectro-photo) is 1000times as large as or more than one of the peak of the Si—NH₂ bondintensity, as a measure for restricting variation of the devicecharacteristics due to hydrogen in the silicon nitride.

Note that a CVD furnace employing a typical remote plasma is disclosedin, for example, Japanese Patent Application Laid-Open: No. 9-181055(the corresponding U.S. patent application Ser. No. 08/570,058 filed onDec. 11, 1995); No. 10-154703 (the corresponding U.S. patent applicationSer. No. 08/748,883 filed on Nov. 13, 1996); No. 10-154706 (thecorresponding U.S. patent application Ser. No. 08/746,631 filed on Nov.13, 1996); No. 10-163184 (the corresponding U.S. patent application Ser.No. 08/748,960 filed on Nov. 13, 1996); No. 10-178004 (the correspondingU.S. patent application Ser. No. 08/748,095 filed on Nov. 13, 1996); No.10-189467 (the corresponding U.S. patent application Ser. No. 08/748,094filed on Nov. 13, 1996); No. 10-256244 (the corresponding U.S. patentapplication Ser. No. 08/747,830 filed on Nov. 13, 1996); No. 11-74097(the corresponding U.S. patent application Ser. No. 08/839,007 filed onApr. 23, 1997); and the like.

DISCLOSURE OF THE INVENTION

A silicon nitride, used in a forming step of a self-align contact, isdeposited by using a butch-type thermal CVD device of a hot wall type,which thermally degrades a silane type gas, such as monosilane (SiH₄) ordichlorosilane (Si₂H₆), and ammonia gas at a high temperature.

However, in a recent fine MISFET, there begins being adopted, as ameasure for preventing a reduction in the threshold values, a so-calleddual gate CMOS (or CMIS (Complementary Metal Insulator Semiconductor))structure in which a gate electrode of an n-channel MISFET is made ofn-type polycrystal silicon and a gate electrode of a p-channel MISFET ismade of p-type polycrystal silicon and both electrodes are used as asurface channel type.

In this case, there is the danger that, when a thermal treatment at ahigh temperature is applied in a step after the gate electrode areformed, p-type impurities (boron) in the gate electrode made of p-typepolycrystal silicon are diffused into a semiconductor substrate (well)through a gate oxide film and the threshold voltage of the MISFET isvaried. Therefore, it is required that a thermal degradation temperatureof a source gas is lowered if a silicon nitride is deposited in the stepafter the gate electrodes are formed.

Further, it is required that pn junctions, constructing a source anddrain, are formed in a shallow manner in order to improve operationcharacteristics of the fine MISFET. However, since when a thermaltreatment at a high temperature is applied in a step after the sourceand drain are formed, impurities in the source and drain areas arediffused and the pn junctions are widened, it is required that a thermaldegradation temperature of the source gas is lowered also when thesilicon nitride is deposited in the step after the source and drain areformed.

However, since a high temperature of about 800° C. or more is requiredto completely degrade Si—H bonds in a silane type gas or N—H bonds in anammonia gas, a large amount of un-degraded Si—H bonds or N—H bondscontaining hydrogen is taken into the silicon nitride if the thermaldegradation temperature of the source gas is lowered. Therefore, thedeterioration of the transistor characteristics as pointed out in theabove prior art is caused.

As a measure therefor, it is proposed that a plasma CVD device capableof forming films at a relatively low temperature (about 400° C.) is usedto plasma-degrade the source gas without hydrogen in a molecular,whereby the amount of hydrogen contained in the silicon nitride islowered. Or, it is proposed that a RF power of plasma is increased tocompletely degrade the silane type gas. However, since when the plasmaCVD device method is applied to a step immediately after the gateelectrode are formed, the surface of the substrate and the gateinsulator are damaged due to the plasma, whereby the deterioration ofthe transistor characteristics is feared. Further, since the plasma CVDmethod has lower coverage characteristics of the film as compared with athermal CVD method, it is difficult to deposit a silicon nitride havinga desired thickness in a gap between the fine gate electrodes.

An object of the present invention is to provide a technique capable of,when a silicon nitride is deposited by a thermal CVD method on asemiconductor wafer having a non-dense area and a dense area of apattern intensity, reducing a film thickness difference between therespective deposited silicon nitride portions on the non-dense area andthe dense area of the pattern intensity.

An object of the present invention is to provide a technique capable offorming a silicon nitride containing a small amount of hydrogen withoutgiving heat load to a transistor.

Another object of the present invention is to provide a techniquecapable of forming a silicon nitride containing a small amount ofhydrogen without giving plasma damage to a transistor.

Another object of the present invention is to provide a techniquecapable of forming a silicon nitride having preferable step coveragewithout giving heat load and/or plasma damage to a transistor.

The above and other objects and novel features of the present inventionwill be appear from the description of the specification and theaccompanying drawings.

Outlines of the representative ones among the inventions, disclosed inthe present application, will be briefly described as follows.

The manufacturing method of a semiconductor integrated circuit deviseaccording to the present invention comprises the steps of:

-   -   (a) introducing, to a heat processing unit, a source gas        containing a first gas having silicon in a molecular and a        second gas having nitrogen in a molecular, and heat-processing        said source gas at a temperature equal to or more than        respective thermal degradation temperatures of said first and        second gases; and    -   (b) supplying, to a film-forming processing unit, a gas        containing degradation products of said first and second gases        generated in said heat processing unit, and depositing a first        insulator, whose a main component is a silicon nitride, over a        main surface of a semiconductor wafer maintained at a        temperature lower than the thermal degradation temperature of        said source gas.

The manufacturing method of a semiconductor integrated circuit deviceaccording to the present invention comprises the steps of:

-   -   (a) introducing, to a plasma processing unit, a source gas        containing a first gas having silicon in a molecular and a        second gas having nitrogen in a molecular, and plasma-processing        said source gas; and    -   (b) supplying, to a film-forming processing unit, a gas        containing degradation products of said first and second gases        generated in said plasma processing unit, and depositing a first        insulator, whose a main component is a silicon nitride, over a        main surface of a semiconductor wafer.

Further, in the manufacturing method of a semiconductor integratedcircuit device according to the present invention, a concentration ofhydrogen contained in said first silicon nitride is 2×10²¹ atoms/cm³ orless, preferably 1×10²¹ atoms/cm³ or less, more preferably 0.5×10²¹atoms/cm³ or less.

Note that, in this application, a semiconductor integrated circuitdevice includes not only one formed especially over a monocrystalsilicon substrate but also one formed over another substrate such as aSOI (Silicon On Insulator) substrate or a TFT (Thin Film Transistor)liquid crystal manufacturing substrate except when clearly denoted tothe contrary. Further, a wafer means a monocrystal silicon substrate(typically, substantially disk-like shape), a SOI substrate, a glasssubstrate, another insulator or semi-insulator, a semiconductorsubstrate, a complex substrate thereof, or the like used formanufacturing a semiconductor integrated circuit device.

Further, in this application, SiN, Si₃N₄, or silicon nitride means notonly stoichiometric one but also ones generally called as the above insemiconductor industry, for example, composition-changed one (that is,nitrogen-rich one or silicon-rich one), or one containing other elementsuch as one containing a large amount of hydrogen, except when clearlydenoted to the contrary.

Further, a concentration of hydrogen in a silicon nitride definedaccording to the present invention means a concentration in measuring,by the FTIR, hydrogen contained in the film immediately after the filmforming (as depo).

Further, a NBTI lifetime means a product lifetime calculated from theamount of shift of a threshold voltage per time by remaining the productat a temperature of 85° C. and in a state where negative bias is appliedto a gate electrode.

A cold wall type CVD device generally means a CVD device having a systemof heating a wafer at temperature higher than the temperature of aninner peripheral wall of a chamber (resistive heating, inductivelycoupled heating, or lamp heating), wherein a plasma is not directlyused.

Further, in the following embodiments, the number of elements or thelike (including quantity, numeric value, amount, range, and the like) isnot limited to the specific number, but may be more or less than thespecific number, except when clearly denoted and when clearly limited tothe specific number in principle. Furthermore, in the followingembodiments, needless to say, constructing elements (including elementsteps or the like) are not necessarily indispensable except when clearlydenoted and when considered to be clearly indispensable.

Similarly, in the following embodiments, a shape or a positionalrelationship of the constructing elements or the like includes onesubstantially closer or similar to the shape except when clearly denotedand when considered to be clearly different. This is applicable to theabove numeric value and range.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a section view of a principal part of a semiconductorsubstrate showing a manufacturing method for a DRAM-logic hybrid LSIaccording to one embodiment of the present invention.

FIG. 2 is a section view of a principal part of a semiconductorsubstrate showing a manufacturing method for a DRAM-logic hybrid LSIaccording to one embodiment of the present invention.

FIG. 3 is a section view of a principal part of a semiconductorsubstrate showing a manufacturing method for a DRAM-logic hybrid LSIaccording to one embodiment of the present invention.

FIG. 4 is a section view of a principal part of a semiconductorsubstrate showing a manufacturing method for a DRAM-logic hybrid LSIaccording to one embodiment of the present invention.

FIG. 5 is a plane view of a principal part of a semiconductor substrateshowing a manufacturing method for a DRAM-logic hybrid LSI according toone embodiment of the present invention.

FIG. 6 is a section view of a principal part of a semiconductorsubstrate showing a manufacturing method for a DRAM-logic hybrid LSIaccording to one embodiment of the present invention.

FIG. 7 is a section view of a principal part of a semiconductorsubstrate showing a manufacturing method for a DRAM-logic hybrid LSIaccording to one embodiment of the present invention.

FIG. 8 is a section view of a principal part of a semiconductorsubstrate showing a manufacturing method for a DRAM-logic hybrid LSIaccording to one embodiment of the present invention.

FIG. 9 is a section view of a principal part of a semiconductorsubstrate showing a manufacturing method for a DRAM-logic hybrid LSIaccording to one embodiment of the present invention.

FIG. 10 is a schematic diagram showing a principal part of a CVD deviceused in one embodiment of the present invention.

FIG. 11 is a graph showing results where desorption behavior of hydrogenin a silicon nitride, deposited by using a commercially availablereduced pressure CVD device, is evaluated by using a thermal desorptionspectrometry (TDS).

FIG. 12 is a section view of a principal part of a semiconductorsubstrate showing a manufacturing method for a DRAM-logic hybrid LSIaccording to one embodiment of the present invention.

FIG. 13 is a plane view of a principal part of a semiconductor substrateshowing a manufacturing method for a DRAM-logic hybrid LSI according toone embodiment of the present invention.

FIG. 14 is a section view of a principal part of a semiconductorsubstrate showing a manufacturing method for a DRAM-logic hybrid LSIaccording to one embodiment of the present invention.

FIG. 15 is a section view of a principal part of a semiconductorsubstrate showing a manufacturing method for a DRAM-logic hybrid LSIaccording to one embodiment of the present invention.

FIG. 16 is a graph showing results where a relationship between a Si—Hbond concentration and a NBTI lifetime in a silicon nitride covering anupper portion and a sidewall of a gate electrode is evaluated.

FIG. 17 is a section view of a principal part of a semiconductorsubstrate showing a manufacturing method for a DRAM-logic hybrid LSIaccording to one embodiment of the present invention.

FIG. 18 is a section view of a principal part of a semiconductorsubstrate showing a manufacturing method for a DRAM-logic hybrid LSIaccording to one embodiment of the present invention.

FIG. 19 is a section view of a principal part of a semiconductorsubstrate showing a manufacturing method for a DRAM-logic hybrid LSIaccording to one embodiment of the present invention.

FIG. 20 is a plane view of a principal part of a semiconductor substrateshowing a manufacturing method for a DRAM-logic hybrid LSI according toone embodiment of the present invention.

FIG. 21 is a section view of a principal part of a semiconductorsubstrate showing a manufacturing method for a DRAM-logic hybrid LSIaccording to one embodiment of the present invention.

FIG. 22 is a section view of a principal part of a semiconductorsubstrate showing a manufacturing method for a DRAM-logic hybrid LSIaccording to one embodiment of the present invention.

FIG. 23 is a plane view of a principal part of a semiconductor substrateshowing a manufacturing method for a DRAM-logic hybrid LSI according toone embodiment of the present invention.

FIG. 24 is a section view of a principal part of a semiconductorsubstrate showing a manufacturing method for a DRAM-logic hybrid LSIaccording to one embodiment of the present invention.

FIG. 25 is a plane view of a principal part of a semiconductor substrateshowing a manufacturing method for a DRAM-logic hybrid LSI according toone embodiment of the present invention.

FIG. 26 is a section view of a principal part of a semiconductorsubstrate showing a manufacturing method for a DRAM-logic hybrid LSIaccording to one embodiment of the present invention.

FIG. 27 is a plane view of a principal part of a semiconductor substrateshowing a manufacturing method for a DRAM-logic hybrid LSI according toone embodiment of the present invention.

FIG. 28 is a section view of a principal part of a semiconductorsubstrate showing a manufacturing method for a DRAM-logic hybrid LSIaccording to one embodiment of the present invention.

FIG. 29 is a section view of a principal part of a semiconductorsubstrate showing a manufacturing method for a DRAM-logic hybrid LSIaccording to one embodiment of the present invention.

FIG. 30 is a section view of a principal part of a semiconductorsubstrate showing a manufacturing method for a DRAM-logic hybrid LSIaccording to one embodiment of the present invention.

FIG. 31 is a section view of a principal part of a semiconductorsubstrate showing a manufacturing method for a DRAM-logic hybrid LSIaccording to another embodiment of the present invention.

FIG. 32 is a section view of a principal part of a semiconductorsubstrate showing a manufacturing method for a DRAM-logic hybrid LSIaccording to another embodiment of the present invention.

FIG. 33 is a section view of a principal part of a semiconductorsubstrate showing a manufacturing method for a DRAM-logic hybrid LSIaccording to another embodiment of the present invention.

FIG. 34 is a schematic diagram showing a principal part of a CVD deviceused in another embodiment of the present invention.

FIG. 35 is a section view of a principal part of a semiconductorsubstrate showing a manufacturing method for a DRAM-logic hybrid LSIaccording to another embodiment of the present invention.

FIG. 36 is a section view of a principal part of a semiconductorsubstrate showing a manufacturing method for a DRAM-logic hybrid LSIaccording to another embodiment of the present invention.

FIG. 37 is a section view of a principal part of a semiconductorsubstrate showing a manufacturing method for a DRAM-logic hybrid LSIaccording to another embodiment of the present invention.

FIG. 38 is a section view of a principal part of a semiconductorsubstrate showing a manufacturing method for a DRAM-logic hybrid LSIaccording to another embodiment of the present invention.

FIG. 39 is a section view of a principal part of a semiconductorsubstrate showing a manufacturing method for a DRAM-logic hybrid LSIaccording to another embodiment of the present invention.

FIG. 40 is a section view of principal part of a semiconductor substrateshowing a manufacturing method for a flash memory according to anotherembodiment of the present invention.

FIG. 41 is a section view of principal part of a semiconductor substrateshowing a manufacturing method for a flash memory according to anotherembodiment of the present invention.

FIG. 42 is a section view of principal part of a semiconductor substrateshowing a manufacturing method for a flash memory according to anotherembodiment of the present invention.

FIG. 43 is a section view of principal part of a semiconductor substrateshowing a manufacturing method for a flash memory according to anotherembodiment of the present invention.

FIG. 44 is a section view of principal part of a semiconductor substrateshowing a manufacturing method for a flash memory according to anotherembodiment of the present invention.

FIG. 45 is a section view of principal part of a semiconductor substrateshowing a manufacturing method for a flash memory according to anotherembodiment of the present invention.

FIG. 46 is a section view of principal part of a semiconductor substrateshowing a manufacturing method for a flash memory according to anotherembodiment of the present invention.

FIG. 47 is a section view of principal part of a semiconductor substrateshowing a manufacturing method for a flash memory according to anotherembodiment of the present invention.

FIG. 48 is a section view of principal part of a semiconductor substrateshowing a manufacturing method for a flash memory according to anotherembodiment of the present invention.

FIG. 49 is a section view of principal part of a semiconductor substrateshowing a manufacturing method for a flash memory according to anotherembodiment of the present invention.

FIG. 50 is a section view of principal part of a semiconductor substrateshowing a manufacturing method for a flash memory according to anotherembodiment of the present invention.

FIG. 51 is a section view of principal part of a semiconductor substrateshowing a manufacturing method for a flash memory according to anotherembodiment of the present invention.

BEST MODES FOR CARRYING OUT THE INVENTION

Embodiments of the present invention will be below described in detailbased on the drawings. Note that, through all the drawings fordescribing the embodiments, members having the same function are denotedby the same reference symbol and the reciprocation thereof will not beomitted. Additionally, descriptions of the same or similar portions willnot be repeated in principle except when being required.

A semiconductor integrated circuit device according to the presentembodiment is a DRAM-logic hybrid LSI in which a DRAM (Dynamic RandomAccess Memory) and a logic circuit are formed over the samesemiconductor substrate. A manufacturing method for this LSI will bedescribed in order of step using FIGS. 1 to 30. Note that, in eachsection view for explaining the manufacturing method, the left andcenter areas each show a DRAM forming area and the right area shows alogic circuit forming area.

At first, as shown in FIG. 1, a semiconductor substrate (hereinafter,referred to as “substrate”, and sometimes refereed to as “wafer”) 1,made of p-type monocrystal silicon having a specific resistance of, forexample, about 1 to 10 Ωcm, is thermally oxidized at 800 to 850° C., anda silicon oxide (pad oxide film) 2 for the purpose of stress relaxationand for protection of an active region is formed on a main surface ofthe substrate 1, and thereafter a silicon nitride 3 is deposited on thesilicon oxide 2 by a CVD method.

The above silicon nitride 3 is deposited, by a reduced pressure CVDmethod (LP-CVD method) using dichlorosilane (SiH₂Cl₂) and ammonia (NH₃),or monosilane and nitrogen (N₂) as a source gas. Further, since thesilicon nitride 3 requires a relatively large film thickness (forexample, 120 nm), it is desirable that a batch type thermal CVD devicehaving a hot wall furnace is used to simultaneously process, forexample, approximately 50 to 100 substrates 1, thereby improvingthroughput of the film forming. The hot wall type thermal CVD deviceemploys a system of indirectly heating a wafer (radiation heating by aheater outside a tube wall), and has a structure of heating an innerwall of a chamber (reaction chamber) or the entire atmosphere in thechamber to a temperature equal to or more than a degradation temperatureof the source gas.

It is desirable that the source gas is thermally degraded at a hightemperature of 800° C. or more in depositing the above silicon nitride3. When the source gas is thermally degraded at a high temperature of800° C. or more, a Si—H bond and a N—H bond contained in the source gasare substantially completely degraded so that the silicon nitride 3,containing a remarkably small amount of hydrogen, can be obtained. Thus,since the amount of hydrogen diffused from the silicon nitride 3 intothe substrate 1 can be remarkably lowered during a thermal treatmentperformed in the forming step of a shallow groove isolation describedlater, variations of the device characteristics due to hydrogenremaining in the substrate 1 can be securely suppressed.

Next, as shown in FIG. 2, the silicon nitride 3 and the silicon oxide 2in a device isolation region are removed, by dry-etching using aphotoresist film 60 as a mask. Subsequently, after the photoresist film60 is removed, as shown in FIG. 3, a shallow groove isolation 4 isformed at a depth of about 350 nm on the substrate 1 in the deviceisolation area, by dry-etching using the silicon nitride 3 as a mask,and then the substrate 1 is thermally oxidized at approximately 950° C.to form a silicon oxide 5 at an inner wall of the shallow grooveisolation 4. The silicon oxide 5 is formed, for recovering etchingdamages occurring at the inner wall of the shallow groove isolation 4and for relaxing a stress of the silicon oxide 5 embedded inside theshallow groove isolation 4 in the next step.

Next, as shown in FIG. 4, after a silicon oxide 7 is deposited over amain surface of the substrate 1 by the CVD method and then the substrate1 is thermally processed at approximately 1000° C. to improve filmquality of the silicon oxide 7, a chemical mechanical polishing (CMP)method is used to polish the silicon oxide 7 and to flatten the surfacethereof. In this polishing, the above silicon nitride 3 is used as astopper and the silicon oxide 7 is left only inside the shallow grooveisolation 4. Through the steps so far, the shallow groove isolation 4 iscompleted on the main surface of the substrate 1. As shown in FIG. 5,the above shallow groove isolation 4 are formed, whereby a large numberof active regions L, having elongated island-like patterns surrounded bythe shallow groove isolation 4, is formed on the substrate 1 in the DRAMforming area. Note that the left area of FIG. 4 (and each section viewfor explaining the manufacturing method) is a section taken along theline A-A of FIG. 5, and the center area thereof is a section taken alongthe line B-B.

Next, after the silicon nitride 3, remaining over the main surface ofthe substrate 1, is removed by heat phosphoric acid, as shown in FIG. 6,B (boron) is ion-implanted into parts of the substrate 1 to form ap-type well 8 and P (phosphorus) is ion-implanted into other partsthereof to form an n-type well 9. Subsequently, after the silicon oxide2 remaining on the surface of the substrate 1 is removed by hydrofluoricacid, the substrate 1 is wet-oxidized at approximately 850° C. to form agate insulator 10, made of a clean silicon oxide having a thickness ofapproximately 6 nm, on a surface of the p-type well 8 and a surface ofthe n-type well 9. The gate insulator 10 may be made of a siliconoxynitride, a silicon nitride, a complex insulator of a silicon oxideand a silicon nitride, or the like, instead of the silicon oxide.

Next, as shown in FIG. 7, after a polycrystal silicon 11 having athickness of approximately 70 nm is deposited at an upper portion of thegate insulator 10 by the CVD method, a photoresist film (not shown) isused as a mask to ion-implant P (phosphorus) into the polycrystalsilicon 11 located at an upper portion of the p-type well 8 and toion-implant B (boron) into the polycrystal silicon film 11 located at anupper portion of the n-type well 9. Thus, a conductive type of thepolycrystal silicon 11 is an n-type on the p-type well 8 and a p-type onthe n-type well 9. This ion-implanting is performed so that an n-channelMISFET and a p-channel MISFET constructing the logic circuit becomesurface channel types, respectively.

Next, after a surface of the polycrystal silicon 11 is cleansed byhydrofluoric acid, as shown in FIG. 8, an approximately 7 nm thickWN_(x) film 12 and an approximately 70 nm thick W film are continuouslydeposited on the polycrystal silicon 11 by a sputtering method. TheWN_(x) film 12 functions as a barrier layer for preventing thepolycrystal silicon 11 and the W film 13 from reacting to each other inthe step of thermally processing the substrate 1. Note that a Mo(molybdenum) film may be deposited at an upper portion of the WN_(x)film 12 instead of the W film 13. Further, a silicon film containingapproximately 5% to 50% of Ge (germanium) may be used instead of thepolycrystal silicon 11. When the silicon film contains Ge therein, it isadvantageous that a contact resistance with the upper WN_(x) film 12 canbe reduced because a band gap of silicon is narrowed and/or solidsolubility of impurities is increased. In order to contain Ge insilicon, there is a method of depositing a silicon film containing Ge,by the CVD method using monosilane (SiH₄) and GeH₄, in addition to themethod of ion-implanting Ge into a silicon film.

Next, as shown in FIG. 9, a silicon nitride 14 having a thickness ofapproximately 160 nm is deposited on the W film 13 by the CVD method.This silicon nitride 14 is used as a cap insulator, which covers uppersurfaces of gate electrodes formed in the later step. In the presentembodiment, this silicon nitride 14 is deposited by using the followingdevice.

FIG. 10 is a schematic diagram showing a principal part of a CVD device100 used to deposit the silicon nitride 14. A stage 102 for mounting thewafer (substrate) 1 thereon is provided at the center of a chamber 101of this CVD device 100. A heater (not shown) for heating the wafer 1 ata desired temperature is incorporated in this stage 102. In other words,the chamber 101 of this CVD device 100 does not have a hot wallstructure of heating the entire inside thereof at a uniform temperaturebut a cold wall structure of heating only the wafer 1 on the stage 102.In the cold wall type chamber 101, since the thermally degradedcomponents of the source gas are hardly deposited on the inner wallthereof, the film forming with high throughput can be performed.Further, since the chamber 101 of this CVD device 100 adopts a singlewafer system of mounting the wafer 1 one by one on the stage 102 toperform the film forming, the temperature of the wafer 1 can be set withhigh precision and the film thickness uniformity within the wafersurface is preferable as compared with the butch type thermal CVDdevice.

Note that since the latest single wafer system silicon nitride CVDfurnace and a method therefor are disclosed in Japanese PatentApplication No. 2000-332863 (filed on Oct. 31, 2000) and No. 2000-232191(filed on Jul. 31, 2000) and the like by the present inventors, thedescriptions thereof will not be repeated here.

A hot wall furnace 103 for thermally degrading a source gas is providedabove the chamber 101. The hot wall furnace 103 is made of aheat-resistant material such as quartz or the like, and a heater 104capable of setting the inside of the furnace to a high temperatureatmosphere of approximately 1200° C. at maximum is provided at aperiphery thereof. A source gas, supplied to the hot wall furnace 103through pipes 105 and 106, is thermally degraded in this furnace inadvance, and the degraded components thereof are supplied on the stage102 of the chamber 101 to form a film on the surface of the wafer 1. Thesource gas is, for example, dichlorosilane (SiH₂Cl₂) and ammonia (NH₃).

As described above, since the above CVD device 100 is constructed sothat the hot wall furnace (heat processing unit) 103 for thermallydegrading the source gas and the chamber (film-forming processing unit)101 for forming a film on the surface of the wafer 1 are separated fromeach other, the degradation temperature of the source gas and thetemperature of the wafer 1 can be independently controlled.

FIG. 11 is a graph showing results obtained by using a thermaldesorption spectrometry (TDS) method to evaluate desorption behavior ofhydrogen in a silicon nitride, which is deposited by using a source gasof dichlorosilane (SiH₂Cl₂) and ammonia (NH₃) and a source gas ofmonosilane (SiH₄) and nitrogen (N₂) and by employing a commerciallyavailable reduced pressure CVD device. A horizontal axis indicates thedegradation temperature of the source gas and a vertical axis indicatesthe ionic strength of hydrogen in the film.

As illustrated, the peaks of desorption of hydrogen are confirmed near400° C. and near 750° C. to 800° C. Since the hydrogen in the siliconnitride is considered to be present as a Si—H bond and a N—H bond andthe Si—H bond is smaller than the N—H bond in bond energy, it is assumedthat the desorption near 400° C. is caused by the Si—H bond and thatnear 750° C. to 800° C. is caused by the N—H bond.

From this measurement results, the temperature of the heater 104 inthermally degrading the source gas in the hot wall furnace 103 of theabove CVD device 100 should have a lower limit near 600° C. at which thedesorption of the N—H bond is promoted. More intermediate productscontaining the H—N bond are produced below the temperature, which is notpractical. In order to reduce the produced amount of intermediateproducts containing the N—H bond, the temperature of the heater 104 ispreferably set at 700° C. or more, and more preferably 800° C. or more,whereby the Si—H bond and the N—H bond are substantially completelydegraded.

Meanwhile, since the chamber 101, serving as the film-forming processingunit, is separated from the hot wall furnace 103, the temperature of thestage 102 mounting the wafer 1 thereon can be lowered to a roomtemperature or less even when the temperature of the heater 104 is setat 800° C. or more. Further, since the chamber 101 has the cold wallstructure of heating only the wafer 1 on the stage 102, the reduction ofthroughput in the film forming is small even if the temperature of thestage 102 is set to the low temperature.

A practical lower limit temperature of the stage 102 during the filmforming is in the vicinity of 0° C. However, there is the danger thatthe throughput in the film forming is reduced when the temperature ofthe stage 102 is too low, or that intermediate products of the sourcegas, generated in the hot wall furnace 103, are cooled in the mid-courseof reaching the surface of the wafer 1 to generate impurities.Therefore, the practical lower limit temperature should be preferablyset at 400° C. or more. The upper limit temperature of the stage 102 isthe upper limit of the temperature, which is allowed from the viewpointof the characteristics of a device formed over the main surface of thewafer 1, and since it is different depending on the device, it cannot begenerally defined. However, in the case of the DRAM hybrid LSI accordingto the present embodiment, for example, the temperature is 700° C. to750° C. When the temperature of the stage 102 exceeds this upper limittemperature, there is the danger that B (boron) in the polycrystalsilicon 11 is diffused into the n-type well 9 and the threshold voltageof the p-channel MISFET partially constructing the logic circuit isvaried.

Further, the pressure of the source gas should be set to at least 0.013kPa (0.1 Torr) or more. However, the pressure in the vicinity of 45.5kPa (350 Torr) is generally preferable in consideration of thethroughput in the film forming. Meanwhile, an upper limit of the gaspressure is preferably set at 98.8 kPa (760 Torr) or less inconsideration of safety of the source gas.

The source gas, used for forming the silicon nitride 14, is not limitedto a combination of dichlorosilane (SiH₂Cl₂) and ammonia (NH₃) describedabove, and may use a well-known source gas, which is used for forming asilicon nitride using the reduced pressure CVD (LP-CVD) device, forexample, a combination of a silicon compound generally indicated bySiH_(y)X_((4-y)) (X is halogen such as F, Cl, Br, and I, and y is 0, 1,2, 3, or 4), such as SiH₄ or Si₂H₆, and of NH₃, N₂H₄ or N₂, or the like.

By using a source gas containing no hydrogen in a molecular among theabove silicon compounds, for example, by using a combination of asilicon compound, such as SiF₄, SiCl₄, Si₂Cl₆, SiBr₄, and SiI₄, and ofN₂, the concentration of hydrogen in the silicon nitride can be furtherreduced. When such silicon compound is used, the step coverage isslightly reduced as compared with the case where the source gascontaining hydrogen in a molecular is used. However, since the siliconnitride 14 is deposited on a surface of a flat base, no problem occurs.

Thus, since the source gas can be thermally degraded at a hightemperature of 800° C. or more by using the above CVD device 100, thesilicon nitride 14 having a remarkably low concentration of hydrogen inthe film can be obtained. Further, the temperature of the wafer(substrate) 1 during the film forming can be set at the low temperature,thereby allowing variation in the device characteristics due to heatload to be securely restricted.

Next, as shown in FIG. 12, a photoresist film 61 is used as a mask tosequentially dry-etch the silicon nitride 14, the W film 13, the WN_(x)film 12, and the polycrystal silicon 11, whereby gate electrodes 11 a(word lines WL) are formed over the gate insulator 10 in the DRAMforming area and gate electrodes 11 b and 11 c are formed over the gateinsulator 10 in the logic circuit forming area. The gate electrodes 11 ato 11 c each have the polymetal structure where the WN_(x) film 12 andthe W film 13 are laminated at the upper portion of the polycrystalsilicon 11. As shown in FIG. 13, the gate electrodes 11 a in the DRAMforming area extend in a direction orthogonal to long sides of theactive regions L, and construct the word lines WL in the region otherthan the active regions L. A gate length of each gate electrode 11 a andan interval between the adjacent electrodes 11 a are, for example, 0.13to 1.4 μm.

Next, after the photoresist film 61 is removed, as shown in FIG. 14, As(arsenic) is ion-implanted into the p-type well 8 by using a photoresistfilm (not shown) as a mask and B (boron) is ion-implanted into then-type well 9, whereby n⁻-type semiconductor regions 15 are formed inthe p-type wells 8 and at both sides of each of the gate electrodes 11 aand 11 b and p ⁻-type semiconductor regions 16 are formed in the n-typewell 9 and at both sides of the gate electrode 11 c.

Next, as shown in FIG. 15, an approximately 50 nm thick silicon nitride17, covering the upper portions and the sidewalls of the gate electrodes11 a, 11 b, and 11 c, is deposited. This silicon nitride 17 is depositedby using the CVD device 100 used for depositing the above siliconnitride 14, and the film-forming conditions (temperatures of the heater104 and the stage 102, and type and pressure of the source gas) are setto be identical to the film-forming conditions of the silicon nitride14. Thus, the silicon nitride 17, having a remarkably low concentrationof hydrogen in the film, can be obtained similarly to the above siliconnitride film 14, and the variation of the device characteristics due toheat load can be securely restricted.

FIG. 16 is a graph showing results obtained by evaluating a relationshipbetween a Si—H bond concentration and a NBTI lifetime (time when athreshold voltage is shifted by 20 mV), in the silicon nitride coveringthe upper portions and the sidewalls of the gate electrodes. The siliconnitride is deposited by using monosilane (SiH₄) and ammonia (NH₃) as asource gas and by using a commercially available reduced pressure CVDdevice, and the Si—H bond concentration in the film is measured by usinga Fourier transform infrared spectrophotometer (FTIR). Further, asilicon nitride, deposited by using monosilane (SiH₄) and nitrogen (N₂)as a source gas and by using the commercially available plasma CVDdevice, is also subjected to similar evaluation.

As a result, it has been found that the NBTI lifetime correlates withthe Si—H bond concentration in the silicon nitride and is reduced inproportion to the Si—H bond concentration to the 1.2th power. From thisfact, in the case of the above silicon nitride 14 covering the upperportions of the gate electrodes 11 a, 11 b, and 11 c or the siliconnitride 17 covering the sidewalls thereof, the concentration of hydrogenimmediately after the film forming is set at 2×10²¹ atoms/cm³ or less,preferably 1×10²¹ atoms/cm³ or less, and more preferably 0.5×10²¹atoms/cm³ or less, thereby securely improving the NBTI lifetime of thedevice.

Next, as shown in FIG. 17, the substrate 1 in the DRAM forming area iscovered with a photoresist film (not shown) and the silicon nitride 17in the circuit unit is anisotropically etched, whereby sidewall spacers(sidewall insulators) 17 s are formed at the sidewalls of the gateelectrodes 11 b and 11 c in the logic circuit forming area.Subsequently, a photoresist film (not shown) is used as a mask toion-implant As (arsenic) into the p-type well 8 in the logic circuitforming area and to ion-implant B (boron) into the n-type well 9,whereby n⁺-type semiconductor regions (source and drain) 18 are formedin the p-type well 8 at both sides of each of the gate electrodes 11 aand 11 b and p ⁺-type semiconductor regions (source and drain) 19 areformed in the n-type well 9 at both sides of the gate electrode 11 c.Through the steps so far, an n-channel MISFET Qn and a p-channel MISFETQp constructing the logic circuit are completed.

Next, as shown in FIG. 18, an interlayer insulator 20, made of, forexample, a spin-on-glass and a double-layered silicon oxide, is formedover the upper portions of the gate electrodes 11 a to 11 c. In order toform the interlayer insulator 20, the spin-on-glass is firstspin-applied on the upper portions of the gate electrodes 11 a to 11 c.Since the spin-on-glass is excellent in gap fill characteristics betweenfine wirings as compared with a silicon oxide deposited by the CVDmethod, even if the interval between the gate electrodes 11 a (wordlines WL) in the DRAM forming area is remarkably narrow, the intervalcan be preferably embedded. Next, after a silicon oxide is deposited onthe spin-on-glass by the CVD method, this silicon oxide is polished andflattened by the chemical mechanical polishing method. Next, asecond-layer silicon oxide is deposited on the polished and flatteredsilicon oxide by the CVD method in order to correct fine damages(micro-scratches) on the surface of the silicon oxide having occurred inbeing polished by the chemical mechanical polishing method.

Next, as shown in FIGS. 19 and 20, an interlayer insulator 20 at theupper portions of the n⁻-type semiconductor regions 15 and in the DRAMforming area is removed by dry-etching using a photoresist film (notshown) as a mask. This etching is performed under the condition that theetching rate of the interlayer insulator 20 (the spin-on-glass and thesilicon oxide) to the silicon nitrides 14 and 17 is made larger.

Subsequently, the silicon nitride 17 on the n⁻-type semiconductorregions 15 is removed by dry-etching using the photoresist film as amask and the surfaces of the n⁻-type semiconductor regions 15 areexposed, whereby contact holes 21 and 22 are formed. A part of thecontact hole 21 extends on the shallow groove isolation 4 off the activeregion L.

The etching of the above silicon nitride film 17 is performed under thecondition that the etching rate of the silicon nitride 17 to the siliconoxide 7 embedded in the shallow groove isolation 4 is made larger sothat the shallow groove isolation 4 is not deeply grinded. Further, thisetching is performed under the condition that the silicon nitride 17 isanisotropically etched so that the silicon nitride 17 is left at thesidewalls of the gate electrodes 11 a (word lines WL). Thus, the contactholes 21 and 22, each having a fine diameter, are formed for the gateelectrodes 11 a (word lines WL) in a self-align manner.

Next, as shown in FIG. 21, plugs 23 are formed inside the contact holes21 and 22. In order to form the plugs 23, a low-resistant polycrystalsilicon, in which P is doped, is deposited, by the CVD method, insidethe contact holes 21 and 22 and at the upper portion of the interlayerinsulator 20 and, subsequently, an unnecessary polycrystal silicon onthe interlayer insulator 20 is removed by dry-etching.

Next, the substrate 1 is thermally processed in the nitrogen gasatmosphere and P in the polycrystal silicon constructing the plugs 23 isdiffused into the n⁻-type semiconductor regions 15, whereby thelow-resistance source and drain is formed. Through the steps so far, amemory cell selection MISFET Qt is formed in the DRAM forming area.

Next, as shown in FIGS. 22 and 23, after a silicon oxide 24 is depositedat the upper portion of the interlayer insulator 20 by the CVD method,the silicon oxide 24 in the logic circuit forming area and theunderlying interlayer insulator 20 below the same are dry-etched bydry-etching using a photoresist film (not shown) as a mask, wherebycontact holes 25 are formed on the source and drain (n⁺-typesemiconductor regions 18) of the n-channel MISFET Qn and contact holes26 are formed on the source and drain (p⁺-type semiconductor regions 13)of the p-channel MISFET Qp. Further, the silicon oxide 24 in the DRAMforming area is etched to form through holes 27 on the contact holes 21.

Next, as shown in FIGS. 24 and. 25, after plugs 28 are formed inside theabove contact holes 25, 26, and 27, bit lines BL are formed on thesilicon oxide 24 in the DRAM forming area and wirings 30 to 33 areformed on the silicon oxide 24 in the logic circuit forming area.

In order to form the plugs 28, for example, a TiN film and a W film aredeposited, on the silicon oxide film including the respective insides ofthe contact holes 25 and 26 and the through hole 27, by the sputteringmethod and the CVD method. Thereafter, unnecessary W film and TiN filmon the silicon oxide 24 are removed by the chemical mechanical polishingmethod. Further, to form the bit lines BL and the wirings 30 to 33,after a W film is deposited on the silicon oxide 24 by the sputteringmethod, the W film is patterned by dry-etching using a photoresist filmas a mask. The bit line BL is electrically connected to one (n⁻-typesemiconductor region 15) of the source and drain of the memory cellselection MISFET Qt through the through hole 27 and the contact hole 21.Further, the wirings 30 and 31 are electrically connected to the sourceand drain (n⁺-type semiconductor regions 18) of the n-channel MISFET Qnthrough the contact holes 25 and 25, and the wirings 32 and 33 areelectrically connected to the source and drain (p⁺-type semiconductorregions 19) of the p-channel MISFET Qp through the contact holes 26 and26.

Next, as shown in FIGS. 26 and 27, a silicon oxide 35 is deposited onthe bit lines BL and the wirings 30 to 33 by the CVD method, andsubsequently the silicon oxides 35 and 24 on the contact holes 22 aredry-etched to form through holes 36, and then plugs 37 made of apolycrystal silicon are formed inside the through holes 36. In order toform the plugs 37, after a polycrystal silicon, in which P (phosphorus)is doped, is deposited inside the through holes 36 and on the siliconoxide 35 by the CVD method, an unnecessary polycrystal silicon on thesilicon oxide 35 is removed by dry-etching (or chemical mechanicalpolishing method).

Next, as shown in FIG. 28, after a silicon nitride 38 is deposited at anupper portion of the silicon oxide 35 by the CVD method and subsequentlya silicon oxide 39 is deposited at an upper portion of the siliconnitride 38 by the CVD method, the silicon oxide 39 and the siliconnitride 38 on the through holes 36 are dry-etched to form grooves 40.

Next, as shown in FIG. 29, lower electrodes 41 made of a polycrystalsilicon are formed on inner walls of the grooves 40. In order to formthe lower electrode 41, after an amorphous silicon film (not shown), inwhich P (phosphorus) is doped, is deposited inside the grooves 40 and onthe silicon oxide 39 by the CVD method, an unnecessary amorphous siliconfilm on the silicon oxide 39 is removed by dry-etching. Next, after asurface of the amorphous silicon remaining inside the grooves 40 iswet-cleaned by a hydrofluoric acid based cleaning liquid, monosilane(SiH₄) is supplied on the surface of the amorphous silicon in a reducedpressure atmosphere. Subsequently, the substrate 1 is thermallyprocessed to polycrystalize the amorphous silicon film and to growsilicon particles on the surface thereof. Thus, the lower electrodes 41,each made of the polycrystal silicon whose the surface is made coarse,are formed. Since the polycrystal silicon, whose surface is made coarse,has a large surface area, the amount of charges stored in a fineinformation storage capacitive element can be increased.

Next, as shown in FIG. 30, a capacity insulator 42 made of a Ta₂O₅(tantalum oxide) film is formed, on the lower electrodes 41 formedinside the grooves 40, and upper electrodes 43 each made of a TiN filmare formed on the capacity insulator 42, whereby information storagecapacitive elements C, each comprising the lower electrode 41, thecapacity insulator 42, and the upper electrode 43, are formed. Thecapacity insulator 42 of the information storage capacitive element Cmay be made of a film whose the main component is high dielectrics orferroelectrics having a perovskite structure or a complex perovskitecrystal structure, such as PZT, PLT, PLZT, PbTiO₃, SrTiO₃, BaTiO₃, BST,SBT or Ta₂O₅ in addition to a Ta₂O₅ film. Through the steps so far, aDRAM memory cell, comprising the memory cell selection MISFET Qt and theinformation storage capacitive element C connected in series thereto, iscompleted.

Although illustration is omitted, thereafter, about two layers of AIwirings are formed on the information storage capacitive elements C bysandwiching the interlayer insulator made of a silicon oxide. Further, apassivation film, comprising a laminated film of a silicon nitride and asilicon oxide, is formed on the AI wirings, whereby the DRAM accordingto the present embodiment is completed. Since the silicon nitrideconstructing a part of the passivation film is deposited at a thicknessof 1 μm or more, the film forming with high throughput is required.Further, in a step after the memory cell selection MISFET Qt or theinformation storage capacitive element C are formed, it is required thatthe film forming is performed at the low temperature. Therefore, thesilicon nitride, constructing the part of the passivation film, isformed at a low temperature of approximately 400° C. by using not theCVD device shown in FIG. 10 but the well-known butch-type plasma CVDdevice.

Second Embodiment

A semiconductor integrated circuit device according to the presentembodiment is a CMOS-logic LSI. A manufacturing method for this LSI willbe described in order of step using FIGS. 31 to 39.

As shown in FIG. 31, at first the shallow groove isolation 4, the p-typewell 8, and the n-type well 9 are formed on the substrate 1 by thesimilar method to the first embodiment. Next, after the surface of thesubstrate 1 is cleansed by wet-etching using hydrofluoric acid, as shownin FIG. 32, the substrate 1 is thermally oxidized at approximately 800°C. to 850° C. to form the clean gate insulator 10 over the respectivesurfaces of the p-type well 8 and the n-type well 9 and sequentially toform electrodes 11 d and 11 e on the gate insulator 10. The gateelectrodes 11 d and 11 e are formed by: depositing a polycrystal siliconhaving a thickness of approximately 200 nm to 250 nm, on the gateinsulator 10 by the CVD method; subsequently ion-implanting n-typeimpurities (phosphorus) into a part of the polycrystal silicon;ion-implanting p-type impurities (boron) into other part thereof; andthereafter using a photoresist film as a mask to dry-etch thepolycrystal silicon. The gate electrode lid is made of an n-typepolycrystal silicon, in which phosphorus is doped, and is used as a gateelectrode of the n-channel MISFET (Qn) constructing a part of the logiccircuit. The gate electrode lie is made of a p-type polycrystal silicon,in which boron is doped, and is used as a gate electrode of thep-channel MISFET (Qp) constructing a part of the logic circuit.

Next, as shown in FIG. 33, phosphorus or arsenic (As) is ion-implantedinto the p-type well 8 to form the n⁻-type semiconductor regions 15having a low impurity concentration, and boron is ion-implanted into then-type well 9 to form the p⁻-type semiconductor regions 16 having a lowimpurity concentration. Thereafter, a silicon nitride 29 having athickness of approximately 50 nm is deposited over the main surface ofthe substrate 1 by the CVD method. In the present embodiment, thissilicon nitride 29 is deposited by using the following device.

FIG. 34 is a schematic diagram showing a principal part of a CVD device200 used for depositing the silicon nitride 29. The CVD device 200 isprovided with a remote plasma unit (plasma processing unit) 202 forgenerating plasma by utilizing microwaves, outside the chamber 201serving as the film-forming processing unit. A source gas is radicallydegraded in this remote plasma unit 202, and then is introduced into thechamber 201. The chamber 201 has the cold wall structure where only thewafer 1 on the stage 203 is heated similarly to the CVD device 100 ofthe first embodiment.

In this manner, since the above CVD device 200 has the structure wherethe remote plasma unit 202 for plasma-degrading the source gas and thechamber 201 are separated from each other, the wafer 1 on the stage 203is hardly influenced by plasma. That is, since it is possible to set RFpower to be high (for example, a frequency of 400 kHz, an output of 5 kWor more) and to promote degradation of the source gas withoutconsidering damage on the wafer 1, the Si—H bond and the N—H bond in thesource gas can be substantially completely degraded. Therefore, it isnot required that the temperature of the wafer 1 is set to be high,thereby allowing heat load of the device to be reduced. Further, sincebias is not applied on the wafer 1 unlike the existing plasma CVDdevice, the film forming with high step coverage can be achieved.

A practical lower limit temperature of the stage 203 during the filmforming is in the vicinity of 0° C. However, there is the danger thatthe throughput in the film forming is reduced when the temperature ofthe stage 203 is too low, or that intermediate products of the sourcegas, generated in the remote plasma unit 202, are cooled in themid-course of reaching the surface of the wafer 1 to generateimpurities. Therefore, the lower limit temperature should be preferablyset at 400° C. or more. An upper limit temperature of the stage 203 isan upper limit temperature, which is allowed from the viewpoint of thecharacteristics of the device formed over the main surface of the wafer1, and is set at, for example, 700° C. to 750° C. in the case of theCMOS logic LSI according to the present embodiment.

The inner wall of the chamber 201 is maintained, for example, at 100° C.or less. Since the temperature of the inner wall is made lower so thatradicals introduced into the chamber 201 are difficult to attach on theinner wall, the film-forming rate is increased. Thus, even if thetemperature of the stage 203 is lowered, the film forming can beperformed in a short time, whereby the heat load of the device can befurther reduced.

A pressure of the source gas is in a range of 0.013 kPa (0.1 Torr) ormore to 1.3 kPa (10 Torr) or less, and is preferably in the vicinity of0.2 kPa (0.5 Torr) generally.

The source gas used for forming the silicon nitride 14 may be awell-known source gas used for forming a silicon nitride by using thereduced pressure CVD (LP-CVD) device, for example, a combination of asilicon compound generally indicated by SiH_(y)X_((4-y)) (X is halogensuch as F, Cl, Br, and I, and y is 0, 1, 2, 3, or 4) such as SiH₄ orSi₂H₆, and of NH₃, N₂H₄ or N₂, or the like. When the source gascontaining no hydrogen in a molecular among the above silicon compounds,for example, a combination of a silicon compound such as SiF₄, SiCl₄,Si₂Cl₆, SiBr₄, and SiI₄, and of N₂ is used, a concentration of hydrogenin the silicon nitride can be further reduced.

Since the above CVD device 200 is used to deposit the silicon nitride12, the concentration of hydrogen in contained the film immediatelyafter the film forming can be set at 2×10²¹ atoms/cm³ or less,preferably at 1×10²¹ atoms/cm³ or less, and more preferably at 0.5×10²¹atoms/cm³, thereby allowing the NBTI lifetime of the device to besecurely improved.

Next, as shown in FIG. 35, the above silicon nitride 29 isanisotropically dry-etched to form sidewall spacers 29 s are formed onthe respective sidewalls of the gate electrodes lid and lie. Next, asshown in FIG. 36, phosphorous or arsenic (As) is ion-implanted into thep-type well 8 to form the n⁺-type semiconductor regions (source anddrain) 18 having high impurity concentration, and boron is ion-implantedinto the n-type well 9 to form the p⁺-type semiconductor regions (sourceand drain) 19 having high impurity concentration. Subsequently, the gateinsulators 10 on the respective surfaces of the n⁺-type semiconductorregions (source and drain) 18 and the p⁺-type semiconductor regions(source and drain) 19 are removed by wet-etching using hydrofluoricacid. Thereafter, a Co film is deposited over the substrate 1 by thesputtering method, and a Co silicide layer 45 is formed, on therespective surfaces of the gate electrodes 11 d, l1 e, the n⁺-typesemiconductor regions (source and drain) 18, and the p⁺-typesemiconductor regions (source and drain) 19, through a silicide reactionby the thermal processing. Then, the unreacted Co film is removed by thewet-etching. Through the steps so far, the n-channel MISFET Qn and thep-channel MISFET Qp constructing the logic LSI are formed.

Next, as shown in FIG. 37, a silicon nitride 46 having a thickness ofapproximately 50 nm is deposited over the main surface of the substrate1 by the CVD method. This silicon nitride 46 is deposited by using theabove CVD device 200 used for depositing the silicon nitride 29. Thefilm-forming conditions may be identical to the film-forming conditionsof the silicon nitride 46 described above. Further, the silicon nitride29 or the silicon nitride 46 may be deposited by using the CVD device100 according to the first embodiment.

Next, as shown in FIG. 38, after a silicon oxide 47 is deposited on thesilicon nitride 46 by the plasma CVD method using, for example, oxygenand tetraethoxysilane as a source gas, the silicon oxide 47 and thesilicon nitride 46 are sequentially dry-etched by using a photoresistfilm (not shown) as a mask to form contact holes 48 to 51 on the n⁺-typesemiconductor regions (source and drain) 18 and the p⁺-typesemiconductor regions (source and drain) 19.

The dry-etching of the above silicon oxide 47 is performed, by using thesilicon nitride 46 as a stopper, under the condition that the etchingrate of the silicon oxide 47 is larger than that of the silicon nitride46. Further, the etching of the silicon nitride 46 is performed underthe condition that the etching rate thereof is larger than that of thesilicon oxide 7 embedded in the shallow groove isolation 4.

Next, as shown in FIG. 39, a metal film, deposited on the silicon oxide47, is patterned to form a first layer of wirings 52 to 55.

Third Embodiment

A semiconductor integrated circuit device according to the presentembodiment is a flash memory. Hereinafter, one example of amanufacturing method for this flash memory will be described in order ofstep by using FIGS. 40 to 52.

As shown in FIG. 40, at first, after the shallow groove isolation 4, thep-type well 8, and the gate insulator 10 are formed over the mainsurface of the substrate 1 by the similar method to the firstembodiment, as shown in FIGS. 41 and 42, a polycrystal silicon 71 havinga thickness of approximately 70 nm to 100 nm is deposited over thesubstrate 1 by the CVD method. Into the polycrystal silicon 71, n-typeimpurities, for example, phosphorous (P) is doped during the depositingstep thereof. Alternatively, n-type impurities may be doped by anion-implanting method after a non-doped polycrystal silicon isdeposited. The polycrystal silicon 71 is used as a floating gateelectrode of the MISFET constructing the memory cell.

Next, as shown in FIGS. 43 and 44, the polycrystal silicon 71 isdry-etched by using a photoresist film (not shown) as a mask to form, onthe active regions, the polycrystal silicon 71, which has an elongatedstrip-like plane pattern extending along its extending direction.

Next, as shown in FIGS. 45 and 46, an ONO film 72, comprising a siliconoxide, a silicon nitride, and a silicon oxide, is formed over thesubstrate 1 over which the polycrystal silicon 71 is formed. The ONOfilm 72 is used as a second gate insulator of the MISFET constructingthe memory cell, and is formed by, for example, sequentially depositinga 5 nm thick silicon oxide, a 7 nm thick silicon nitride, and a 4 nmthick silicon oxide over the substrate 1 by the CVD method.

Next, as shown in FIGS. 47 and 48, an n-type polycrystal silicon 73 inwhich P (phosphorous) is doped, a WN_(x) film 74, a W film 75, and asilicon nitride 76 are sequentially deposited on the ONO film 67. Thepolycrystal silicon 73, the WN_(x) film 74, and the W film 75 are usedas control gate electrodes (word lines WL) of the MISFET constructingthe memory cell. Further, the silicon nitride 76 is used as an insulatorfor protecting the upper portions of the control gate electrodes. Thepolycrystal silicon 73 may be made of a silicon film containingapproximately 50% of Ge (germanium) at maximum.

The silicon nitride 76 is deposited by using the CVD device 100 in thefirst embodiment or the CVD device 200 in the second embodiment. Thus, aconcentration of hydrogen contained in the film immediately after thefilm forming can be set at 2×10²¹ atoms/cm³ or less, preferably 1×10²¹atoms/cm³ or less, and more preferably 0.5×10²¹ atoms/cm³ or less.

Next, as shown in FIG. 49, the silicon nitride 76, the W film 75, theWN_(x) film 74, the polycrystal silicon 73, the ONO film 72, and thepolycrystal silicon 71 are sequentially dry-etched by using aphotoresist film (not shown) as a mask to form: floating gate electrodes71 f each comprising the polycrystal silicon 71; and control gateelectrodes 77 c (word lines WL) of a polymetal structure of comprisingthe W film 75, the WN_(x) film 74, and the polycrystal silicon 73.

Next, as shown in FIG. 50, n-type semiconductor regions 70, constructingsource and drain of the MISFET, are formed. The n-type semiconductorareas 70 are formed by: ion-implanting n-type impurities (for example,arsenic (As)) into the p-type well 3; thereafter thermally processingthe substrate 1 at about 900° C.; and diffusing the above n-typeimpurities into the p-type well 3.

Next, after the surface of the substrate 1 is cleansed, as shown in FIG.51, a silicon nitride 79 is deposited over the substrate 1. The siliconnitride 79 is deposited by using the CVD device 100 in the firstembodiment or the CVD device 200 in the second embodiment. Thus, theconcentration of hydrogen contained in the film immediately after thefilm forming is set at 2×10²¹ atoms/cm³ or less, preferably 1×10²¹atoms/cm³ or less, and more preferably 0.5×10²¹ atoms/cm³ or less.

As described above, the invention made by the inventors has beenconcretely described based on the embodiments thereof. However, needlessto say, the present invention is not limited to the above-mentionedembodiments and can be variously modified and altered without departingfrom the gist thereof.

Generally, a memory LSI such as a DRAM or a flash memory includes amemory mat and a peripheral circuit in one chip. In the memory mat,MISFETs constructing the memory cell are arranged in a high dense mannerin order to realize a large storage capacity. However, in the peripheralcircuit, the MISFETS are arranged in a non-dense manner as compared withthe memory mat. Therefore, when gate electrodes of the MISFET are formedon the wafer, non-dense regions (peripheral circuit) and dense regions(memory mat) relative to the pattern densities of the gate electrodesoccur in a plurality of chip regions partitioned on the wafer. As aresult, the thickness of the silicon nitride covering the gateelectrodes is different depending on the peripheral circuit and thememory mat.

In the case where the above problem (non-uniformity of the thickness)occurs, the silicon nitride is dry-etched to form the sidewall spacerson the sidewalls of the gate electrodes in the memory mat and on thoseof the gate electrodes in the peripheral circuit, or to form the contactholes for the gate electrodes and/or for the device isolation regions ina self-align manner. At this time, if a thick silicon nitride depositedin the peripheral circuit is completely etched, not only the thinsilicon nitride deposited in the memory mat but also the surface of thebase (the gate oxide film or the substrate) is grinded. Therefore, thecharacteristics of the MISFET, constructing the memory cell, aredegraded.

The CVD device 100 in the first embodiment or the CVD device 200 in thesecond embodiment substantially completely degrades the source gasoutside the chamber in advance, and then supplies the degraded gas tothe surface of the wafer. Therefore, the uniformly thick silicon nitridecan be formed without depending on the pattern densities of the gateelectrodes even if there are the non-dense regions and the dense regionsrelative to the pattern densities of the gate electrodes.

INDUSTRIAL APPLICABILITY

The effects, obtained by the representative ones among the inventionsdisclosed in this application, will be briefly described as follows.

According to one embodiment of the present invention, a silicon nitride,containing a small amount of hydrogen, can be formed without giving heatload on the transistor, thereby allowing the NBTI lifetime of the deviceto be improved.

According to another embodiment of the present invention, a siliconnitride, containing a small amount of hydrogen, can be formed withoutgiving plasma damage to the transistor, thereby allowing the NBTIlifetime of the device to be improved.

1-46. (canceled)
 47. A semiconductor integrated circuit devicecomprising: a MISFET formed over a main surface of a semiconductorsubstrate; and an insulator covering at least a part of a gate electrodeof said MISFET, a main component of the insulator being a siliconnitride formed by a cold wall thermal CVD method, wherein aconcentration of hydrogen contained in said silicon nitride is 2×10²¹atoms/cm³ or less, and said silicon nitride is an etching stopper filmused in forming a contact hole relative to said gate electrode in aself-alignment manner.
 48. The semiconductor integrated circuit deviceaccording to claim 47, wherein a concentration of hydrogen contained insaid silicon nitride is 1×10²¹ atoms/cm³ or less.
 49. The semiconductorintegrated circuit device according to claim 48, wherein a concentrationof hydrogen contained in said silicon nitride is 0.5×10²¹ atoms/cm³ orless.
 50. The semiconductor integrated circuit device according to claim47, wherein said hydrogen is generated by dissociation of a Si—H bondcontained in said silicon nitride.
 51. The semiconductor integratedcircuit device according to claim 47, wherein said silicon nitride isdeposited by a CVD method using a source gas containing a silicon typegas, and ammonia or a nitrogen gas.